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TinyMeasurement · Real-time Acquisition · DMA Dual Core — Design notes

Actual application acquisition chain

flowchart TB
    T[Timer callback] --> N[Notify producer]
    N --> S[Read ADXL355]
    S --> B[Lock and write active buffer]
    B --> F{Buffer full?}
    F -->|Yes| R[Mark ready and switch buffer]
    R --> C[Notify consumer to process and output]
    F -->|No| N

A timer callback notifies the producer task. The awakened producer reads ADXL355 acceleration and temperature, writes samples into a buffer, and notifies the consumer. Locks coordinate buffer switching and shared state. Application sampling is not triggered by a DMA-completion interrupt; SPI driver DMA is a separate layer.

Older sketches below remain as design history. Buffering and task separation overlap acquisition and processing, while memory, buses, locks and network resources remain shared. They do not guarantee zero jitter or maximum throughput. Validate actual sample intervals, dropped/overwritten samples, buffer occupancy and transmission time.

源码 / Source

DMA + Dual Core — Two Cores: Core0 Acquires, Core1 Processes

ESP32-S3 has two cores. This architecture pins acquisition to Core0 and processing to Core1, using double buffering to overlap acquisition and processing.

Intuition

Two-Core Division

Historical DMA sketch (not the current trigger chain)
Core 0 ─── DMA + acquisition (interrupt-driven)
              ↓
        double-buffer switch
              ↓
Core 1 ─── data processing + threshold detection + MQTT output

The tasks divide responsibilities while sharing resources:

  • Core0 acquisition: timer notification → sensor read → buffer write/switch
  • Core1 only processes: read Core0's buffer → feature extraction → threshold → output

Why Not One Core?

On one core, acquisition and processing are serialized: sample a bit, compute a bit, sample a bit. Heavy computation causes jitter in sampling intervals, hurting timing precision.

Dual-core parallelizes acquisition and processing. Shared locks, buses and scheduling can still affect sample timing.

Data Flow

Historical DMA sketch (not the current trigger chain)
Core0 (acquisition):
    DMA interrupt → buffer switch → notify Core1

Core1 (processing):
    wait for notification → read buffer → features → threshold → output

Config

#define TINY_MEASUREMENT_RT_DMA_DC_BUFFER_SIZE 256
#define TINY_MEASUREMENT_RT_DMA_DC_PRODUCER_CORE 0
#define TINY_MEASUREMENT_RT_DMA_DC_CONSUMER_CORE 1

Notes

When to use Dual Core?

When the other two architectures still drop samples. Measure throughput improvements under the target workload.

Careful with resource allocation

WiFi/BLE tasks on Core1 may compete with processing. Dedicate Core1 to processing only; leave network tasks to Core0.